aytas1989
Üye
- Mesajlar
- 13
Merhabalar,
Aşağıdaki konu ile ilgili bilgisi olan var mı? grafikleri tamamlamam gerekiyor, Konuya hakim olamadığım için araştırma yapmakta da zorlanıyorum. İlgili kaynak tavsiyesinde bulunabilir misiniz?
Teşekkürler.
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1. Study and understand how the circuit in Figure 1 works (the appendix describes the 74191).
2. Lets suppose that the content of the lowest memory locations ($000, $001 y $002) is $37, $A9 and
$7E respectively, and that the content of the highest memory location is $00. Suppose also that
the counter initial state is $FFF, and that every component has negligible delay. Complete the
following chronogram:
3. For the previous chronogram, suppose that the logic analyzer captures data at a frequency four
times higher than the circuit board clock frequency. Suppose also that the first capture happens at
the instant marked with an arrow. Mark in the chronogram the instants when the other captures
are carried out and write down the value of the data and address lines in each capture.
4. Complete again the following chronogram, but suppose now that the counter has a delay Rc>0 and
the ROM a delay Rr>0. Suppose also that the sum of both delays is shorter than a half the period
of the board clock (i.e. Rc+Rr < Tp/2, where Tp is the board clock period). Do not forget to highlight
each component delay.
http://hibrahimaytas.com/?page_id=67
5. For the previous chronogram, write down the data and address values that would be captured if
the logic analyzer is configured to capture at the falling edge of the circuit board clock.
6. Complete again the following chronogram supposing that both delays are shorter than a half the
period of the board clock, but its sum is longer (Rc < Tp/2, Rr < Tp/2, Rc+Rr > Tp/2).
http://hibrahimaytas.com/?page_id=67
7. For the previous chronogram, write down the data and address values that would be captured if
the logic analyzer is configured to capture at the falling edge of the circuit board clock.
8. For the previous chronogram, write down the data and address values that would be captured if
the logic analyzer is configured to capture at the rising edge of the circuit board clock.
Aşağıdaki konu ile ilgili bilgisi olan var mı? grafikleri tamamlamam gerekiyor, Konuya hakim olamadığım için araştırma yapmakta da zorlanıyorum. İlgili kaynak tavsiyesinde bulunabilir misiniz?
Teşekkürler.
-----------------------------------------------------------------------------------------------------------
1. Study and understand how the circuit in Figure 1 works (the appendix describes the 74191).
2. Lets suppose that the content of the lowest memory locations ($000, $001 y $002) is $37, $A9 and
$7E respectively, and that the content of the highest memory location is $00. Suppose also that
the counter initial state is $FFF, and that every component has negligible delay. Complete the
following chronogram:
3. For the previous chronogram, suppose that the logic analyzer captures data at a frequency four
times higher than the circuit board clock frequency. Suppose also that the first capture happens at
the instant marked with an arrow. Mark in the chronogram the instants when the other captures
are carried out and write down the value of the data and address lines in each capture.
4. Complete again the following chronogram, but suppose now that the counter has a delay Rc>0 and
the ROM a delay Rr>0. Suppose also that the sum of both delays is shorter than a half the period
of the board clock (i.e. Rc+Rr < Tp/2, where Tp is the board clock period). Do not forget to highlight
each component delay.
http://hibrahimaytas.com/?page_id=67
5. For the previous chronogram, write down the data and address values that would be captured if
the logic analyzer is configured to capture at the falling edge of the circuit board clock.
6. Complete again the following chronogram supposing that both delays are shorter than a half the
period of the board clock, but its sum is longer (Rc < Tp/2, Rr < Tp/2, Rc+Rr > Tp/2).
http://hibrahimaytas.com/?page_id=67
7. For the previous chronogram, write down the data and address values that would be captured if
the logic analyzer is configured to capture at the falling edge of the circuit board clock.
8. For the previous chronogram, write down the data and address values that would be captured if
the logic analyzer is configured to capture at the rising edge of the circuit board clock.